Ad Astra Consultants SerDes Digital Design Engineer

S$8-12K[Monthly]

On-site - CentralFull-time5-10 Yrs ExpBachelor

This job is open to Singaporean/PR, Passholder - EP/SP/WP/Others, Foreigner(excluding Malaysia), Malaysian

Circuit DesignCadenceHardware EngineeringPLC ProgrammingSerDesDDRPCIeVerilog HDLLINT

Participate in high-level product specifications, microarchitecture and implementation of high-speed memory interfaces
Perform RTL coding, LINT checking and sanity testing on implemented designs
Work with the verification team for lab debugging
Work with the software team and/or customers to solve problems, debug and tune system performance

Bachelor's degree in communications, electronic engineering or computer engineering, master’s degree preferred
More than 6 years (staff engineer) and 10 years (senior staff engineer) of ASIC design experience, familiar with ASIC development process
Good Verilog HDL coding skills and EDA tools such as synthesis and timing analysis
Familiarity with high-speed interfaces such as DDR, SerDes, PCIe is preferred
Ability to solve customer problems and deliver results in a timely manner
Strong organizational and communication skills where English is a must and Chinese is preferred